/***************************************************************************
*   Copyright (C) 2010-2011 by swkyer <swkyer@gmail.com>                  *
*                                                                         *
*   This program is free software; you can redistribute it and/or modify  *
*   it under the terms of the GNU General Public License as published by  *
*   the Free Software Foundation; either version 2 of the License, or     *
*   (at your option) any later version.                                   *
*                                                                         *
*   This program is distributed in the hope that it will be useful,       *
*   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
*   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
*   GNU General Public License for more details.                          *
*                                                                         *
*   You should have received a copy of the GNU General Public License     *
*   along with this program; if not, write to the                         *
*   Free Software Foundation, Inc.,                                       *
*   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
***************************************************************************/
#include "stdafx.h"
#include <math.h>
#include "mips32opc.h"
#include "JlinkMIPS.h"
#include "Execution.h"
#include "BreakPoint.h"
#include "CpuInfo.h"


typedef struct _mips32_core_attrib_s
{
    ubase_t cp0_prid;
    ubase_t cp0_config0;
    ubase_t cp0_config1;
    ubase_t cp0_config2;
    ubase_t cp0_config3;
    ubase_t cp0_debug;
    ubase_t ejtag_dcr;
    ubase_t ejtag_ibs;
    ubase_t ejtag_dbs;
} mips32_core_attrib_t;


int mips32_cpuinfo_init(mips32_cpuinfo_t *pcpuinfo, void *pmips32)
{
    pcpuinfo->pmips32 = pmips32;

    pcpuinfo->endian = MIPS_ENDIAN_LITTLE;
    pcpuinfo->hwbpts = MIPS32_DEFAULT_MAX_HWBP;
    pcpuinfo->hwwpts = MIPS32_DEFAULT_MAX_HWWP;
    pcpuinfo->tlb_entries = DEFAULT_TLB_ENTRY_SIZE;

    pcpuinfo->icache.line_size = DEFAULT_ICACHE_LINE_SIZE;
    pcpuinfo->icache.lines_per_way = DEFAULT_ICACHE_LINES_PER_WAY;
    pcpuinfo->icache.ways = DEFAULT_ICACHE_WAYS;
    pcpuinfo->dcache.line_size = DEFAULT_DCACHE_LINE_SIZE;
    pcpuinfo->dcache.lines_per_way = DEFAULT_DCACHE_LINES_PER_WAY;
    pcpuinfo->dcache.ways = DEFAULT_DCACHE_WAYS;

    pcpuinfo->sst_sup= 0;
    pcpuinfo->pcs = 0;

    pcpuinfo->fpu = 0;
    pcpuinfo->sc_impl = 0;

    return 0;
}

int mips32_cpuinfo_exit(mips32_cpuinfo_t *pcpuinfo)
{
    pcpuinfo->pmips32 = NULL;
    return 0;
}

static void get_debug_attrib_info(mips32_core_attrib_t *core_attrib, mips32_cpuinfo_t *pcpuinfo)
{
    uint16_t val;

    val = (core_attrib->cp0_config1 >> 22) & 0x07;
    pcpuinfo->icache.lines_per_way = 64 * (1 << val);
    val = (core_attrib->cp0_config1 >> 19) & 0x07;
    pcpuinfo->icache.line_size = 2 * (1 << val);
    val = (core_attrib->cp0_config1 >> 16) & 0x07;
    pcpuinfo->icache.ways = val + 1;

    val = (core_attrib->cp0_config1 >> 13) & 0x07;
    pcpuinfo->dcache.lines_per_way = 64 * (1 << val);
    val = (core_attrib->cp0_config1 >> 10) & 0x07;
    pcpuinfo->dcache.line_size = 2 * (1 << val);
    val = (core_attrib->cp0_config1 >> 7) & 0x07;
    pcpuinfo->dcache.ways = val + 1;

    val = (core_attrib->cp0_config1 >> 25) & 0x3F;
    pcpuinfo->tlb_entries = val + 1;
    pcpuinfo->sst_sup = (core_attrib->cp0_debug & (1<<9))?0:1;
    pcpuinfo->fpu = core_attrib->cp0_config1 & 0x01;

    val = (core_attrib->cp0_config2 >> 4) & 0x0F;
    pcpuinfo->sc_impl = val?1:0;
    pcpuinfo->scache.line_size = 2 * (1 << val);
    val = (core_attrib->cp0_config2 >> 8) & 0x0F;
    pcpuinfo->scache.lines_per_way = 64 * (1 << val);
    val = (core_attrib->cp0_config1 >> 0) & 0x0F;
    pcpuinfo->scache.ways = val + 1;

    val = (core_attrib->ejtag_ibs >> 24) & 0x07;
    pcpuinfo->hwbpts = val;
    val = (core_attrib->ejtag_dbs >> 24) & 0x07;
    pcpuinfo->hwwpts = val;

    val = (core_attrib->ejtag_dcr >> 29) & 0x01;
    pcpuinfo->endian = val;
    val = (core_attrib->ejtag_dcr >> 9) & 0x01;
    pcpuinfo->pcs = val;
}

int mips32_cpuinfo_probe(mips32_cpuinfo_t *pcpuinfo)
{
    int retv;
    mips32_t *pmips32;
    mips32_exec_context_t *pcontext;

    if (pcpuinfo == NULL)
        return -1;

    pmips32 = (mips32_t *)pcpuinfo->pmips32;
    pcontext = &pmips32->execontext;

    mips32_get_state(pmips32);
    if (pmips32->target_state != CORE_STATE_HALTED)
    {
        // target is running
        return -3;
    }

    retv = mips32_exec_microcode(pcontext, mips32_microcode_probe);
    if (retv < 0)
        return retv;
    get_debug_attrib_info((mips32_core_attrib_t *)pcontext->vram, pcpuinfo);

    return 0;
}
